added some more code to spl.h
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@ -51,7 +51,7 @@ public:
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#if defined(QSE_SUPPORT_SPL)
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SpinLock() QSE_CPP_NOEXCEPT: flag(QSE_SPL_INIT) {}
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#else
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SpinLock() QSE_CPP_NOEXCEPT: flag(0) {}
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SpinLock() QSE_CPP_NOEXCEPT: flag(ATOMIC_FLAG_INIT) {}
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#endif
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bool tryock() QSE_CPP_NOEXCEPT
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@ -135,6 +135,56 @@ asm void qse_spl_unlock (qse_spl_t* spl)
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}
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#endif
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#elif defined(__GNUC__) && (defined(__x86_64) || defined(__amd64) || defined(__i386) || defined(i386))
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static QSE_INLINE int qse_spl_trylock (qse_spl_t* spl)
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{
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register int x = 1;
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__asm__ volatile (
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"xchgl %0, (%2)\n"
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: "=r"(x)
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: "0"(x), "r"(spl)
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: "memory"
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);
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return !x;
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}
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static QSE_INLINE void qse_spl_lock (qse_spl_t* spl)
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{
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register int x = 1;
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do
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{
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__asm__ volatile (
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"xchgl %0, (%2)\n"
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: "=r"(x)
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: "0"(x), "r"(spl)
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: "memory"
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);
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}
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while (x);
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}
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static QSE_INLINE void qse_spl_unlock (qse_spl_t* spl)
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{
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#if defined(__x86_64) || defined(__amd64)
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__asm__ volatile (
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"mfence\n\t"
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"movl $0, (%0)\n"
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:
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:"r"(spl)
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:"memory"
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);
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#else
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__asm__ volatile (
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"movl $0, (%0)\n"
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:
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:"r"(spl)
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:"memory"
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);
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#endif
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}
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#elif defined(QSE_SPL_NO_UNSUPPORTED_ERROR)
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/* don't raise the compile time error */
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#undef QSE_SUPPORT_SPL
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@ -34,7 +34,7 @@ static int thr_func (qse_thr_t* thr, void* ctx)
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qse_printf (QSE_T("%s: [% 16d] [% 16d] [% 16d]\n"), xtn->name, i, i, i);
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qse_spl_unlock (xtn->spl);
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i++;
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//sleep (1);
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/*sleep (1);*/
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}
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return i;
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